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QL6325E Eclipse-E Data Sheet
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FPGA Combining Performance, Density, and Embedded RAM
Device Highlights
Flexible Programmable Logic
* 0.18 m six layer metal CMOS process * 1.8/2.5/3.3 V drive capable I/O * 1536 logic cells * Up to 4,002 flip-flops * Up to 310 I/O pins * Up to 335 user-available pins * 320,460 maximum system gates
Advanced Clock Network
* Nine global clock networks: One dedicated Eight programmable * 20 quad-net networks--five per quadrant * 16 I/O controls--two per I/O bank * Four phase locked loops
Embedded Computational Units
Twelve ECUs provide integrated Multiply, Add, and Accumulate functions.
Embedded Dual Port SRAM
* Twenty-four 2,304-bit dual port high performance SRAM blocks * 55,296 RAM bits * RAM/ROM/FIFO wizard for automatic configuration * Configurable and cascadable
Security Features
The QuickLogic products come with secure ViaLink technology that protects intellectual property from design theft and reverse engineering. No external configuration memory needed; instant-on at power-up. Figure 1: QL6325E Eclipse-E Block Diagram
PLL Embedded RAM Blocks Embeded Computational Units PLL
Programmable I/O
* High performance I/O cell * Programmable slew rate control * Programmable I/O standards: LVTTL, LVCMOS, LVCMOS18, PCI, GTL+, SSTL2, and SSTL3 Eight independent I/O banks Three register configurations: Input, Output, and Output Enable
Fabric
PLL
Embedded RAM Blocks
PLL
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QL6325E Eclipse-E Data Sheet Rev. F
QuickWorks Design Software
The QuickWorks package provides the most complete ESP and FPGA software solution from design entry to logic synthesis, to place and route, to power calculation, and simulation. The package provides a solution for designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other thirdparty tools for design entry, synthesis, or simulation.
Programmable Logic Architectural Overview
The Eclipse-E logic cell structure is presented in Figure 2. This architectural feature addresses today's registerintensive designs. Table 1: Performance Standards
Function Multiplexer Parity Tree Counter Description 16:1 24 36 16 bit 32 bit 128 x 32 FIFO Clock-to-Out System clock 128 x 64 256 x 16 Slowest Speed Grade 2.8 ns 3.4 ns 4.6 ns 275 MHz 250 MHz 197 MHz 188 MHz 208 MHz 4 ns 200 MHz Fastest Speed Grade 2.4 ns 2.9 ns 3.9 ns 328 MHz 300 MHz 235 MHz 266 MHz 248 MHz 3.3 ns 300 MHz
The Eclipse-E logic cell structure presented in Figure 2 is a dual register, multiplexor-based logic cell. It is designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly from a dedicated input. NOTE: The input PP is not an "input" in the classical sense. It is a static input to the logic cell and selects which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can be connected to multiple routing channels. The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay.
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 2: Eclipse-E Logic Cell
QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC QR
AZ
OZ
QZ
NZ Q2Z
FZ
RAM Modules
The QL6325E includes 24 dual-port 2,304-bit RAM modules for implementing RAM, ROM, and FIFO functions. Each module is user-configurable into four different block organizations and can be cascaded horizontally to increase their effective width, or vertically to increase their effective depth as shown in Figure 4. Figure 3: 2,304-bit RAM Module
MODE[1:0] WA[9:0] WD[17:0] WE WCLK
ASYNCRD RA[9:0] RD[17:0] RE RCLK
Using the two "mode" pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are also easily cascadable to increase their effective width and/or depth (see Figure 4).
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 4: Cascaded RAM Modules
WDATA WADDR
RAM Module (2,304 bits)
RDATA RADDR
WDATA
RAM Module (2,304 bits)
RDATA
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. A similar technique can be used to create depths greater than 256 words. In this case address signals higher than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals. The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with data from an external PROM (typically for ROM functions).
Embedded Computational Unit (ECU)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively-- these functions require high logic cell usage while garnering only moderate performance results. The Eclipse-E architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the Eclipse-E device can address various arithmetic functions efficiently. This approach offers greater performance and utilization than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in Figure 5.
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 5: ECU Block Diagram
RESET D S1 S2 S3 CIN SIGN1 SIGN2 00 01 3-1 mux 10 Q[16:0] 3-4 decoder C B A
A[7:0] A[15:8]
8-bit Multiplier
2-1 mux
16-bit Adder
D
Q 17-bit Register
A[0:15] CLK B[0:15] 2-1 mux
The Eclipse-E ECU block (Table 2) is placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations.
Table 2: Eclipse-E ECU Block
Device QL6325E ECUs 12
Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1.2 billion MACs/s when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic. The modes for the ECU block are dynamically re-programmable through the programmable logic.
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QL6325E Eclipse-E Data Sheet Rev. F
Table 3: ECU Mode Select Criteria
Instruction S1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Operation Multiply Multiply-Add Accumulate Add Multiply (registered)c Multiply- Add (registered) Multiply - Accumulate Add (registered)
b
ECU Performancea,
t
-8 WCC
t
PD
t
SU
CO
6.6 ns max 8.8 ns max 3.9 ns min 3.1 ns max 9.6 ns min 9.6 ns min 9.6 ns min 3.9 ns min 1.2 ns max 1.2 ns max 1.2 ns max 1.2 ns max 1.2 ns max
a. tPD, tSU and tCO do not include routing paths in/out of the ECU block. b. Internal feedback path in ECU restricts max clk frequency to 238 MHz. c. B [15:0] set to zero.
NOTE: Timing numbers in Table 3 represent -8 Worst Case Commercial conditions.
Phase Locked Loop (PLL) Information
Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models (described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other PLLs. These PLLs also have the ability to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. When PLLs are cascaded, the clock signal must be routed off-chip through the PLLPAD_OUT pin prior to routing into another PLL; internal routing cannot be used for cascading PLLs. Figure 6 illustrates a QuickLogic PLL. Figure 6: PLL Block Diagram
1st Quadrant 2nd Quadrant 3rd Quadrant FIN Frequency Divide _ .1 . . _2 . . _4 . + Filter vco PLL Bypass 4th Quadrant Clock Tree
Frequency Multiply .1 _ . . _2 . . _4 . FOUT
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QL6325E Eclipse-E Data Sheet Rev. F
Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself. Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in Figure 6) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter (Figure 6). The charge pump generates an error voltage to bring the VCO back into alignment, and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry. Fout represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained in Table 5). The PLL always drives the PLLPAD_OUT signal, regardless of whether the PLL is configured for on-chip use. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down. Most QuickLogic products contain four PLLs. The PLL presented in Figure 6 controls the clock tree in the fourth quadrant of its FPGA. QuickLogic PLLs compensate for the additional delay created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the feedback path.
PLL Modes of Operation
QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency-- Table 4 indicates the features of each mode. NOTE: "HF" stands for "high frequency" and "LF" stands for "low frequency." Table 4: PLL Mode Frequencies
PLL Model PLL_HF PLL_LF PLL_MULT2HF PLL_MULT2LF PLL_DIV2HF PLL_DIV2LF PLL_MULT4 PLL_DIV4 Output Frequency Same as input Same as input 2x 2x 1/2x 1/2x 4x 1/4x Input Frequency Range 66 MHz-220 MHz 25 MHz-66 MHz 33 MHz-110 MHz 12.5 MHz-33 MHz 220 MHz-440 MHz 50 MHz-220 MHz 12.5 MHz-50 MHz 100 MHz-440 MHz Output Frequency Range 66 MHz-220 MHz 25 MHz-66 MHz 66 MHz-220 MHz 25 MHz-66 MHz 110 MHz-220 MHz 25 MHz-110 MHz 50 MHz-200 MHz 25 MHz-110 MHz
The input frequency can range from 12.5 MHz to 440 MHz, while output frequency ranges from 25 MHz to 220 MHz. When adding PLLs to the top-level design, be sure that the PLL mode matches the desired input and output frequencies.
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QL6325E Eclipse-E Data Sheet Rev. F
PLL Signals
Table 5 summarizes the key signals in QuickLogic PLLs. Table 5: QuickLogic PLL Signals
Signal Name PLLCLK_IN PLL_RESET ONn_OFFCHIP CLKNET_OUT PLLCLK_OUT PLLPAD_OUT Input clock signal. Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. This is a reserved signal. It can be connected to VCC or GND. Out to internal gates This signal bypasses the PLL logic before driving the clock tree. Note that this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT). Out from PLL to internal gates This signal can drive the clock tree after going through the PLL. Out to off-chip This outgoing signal is used off-chip. The PLLPAD_OUT is always active, driving the PLL-derived clock signal out through the pad. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down. Description
Active High Lock detection signal LOCK_DETECT NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the PLL_RESET signal.
NOTE: Because PLLCLK_IN and PLL_RESET signals have PLL_INPAD, and PLLPAD_OUT has OUTPAD, you do not need to add additional pads to your design.
I/O Cell Structure
Eclipse-E features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-directional I/O pins and input-only pins. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and comply with the specific I/O standard selected. For single ended I/O standards, VCCIO specifies the input tolerance and the output drive. For voltage referenced I/O standards (e.g SSTL), the voltage supplied to the INREF pins in each bank specifies the input switch point. For example, the VCCIO pins must be tied to a 3.3 V supply to provide 3.3 V compliance. Eclipse-E can also support the LVDS and LVPECL I/O standards with the use of external resistors (see Table 6). Table 6: I/O Standards and Applications
I/O Standard LVTTL LVCMOS25 LVCMOS18 PCI GTL+ SSTL3 SSTL2 Reference Voltage n/a n/a n/a n/a 1 1.5 1.25 Output Voltage 3.3 V 2.5 V 1.8 V 3.3 V n/a 3.3 V 2.5 V Application General Purpose General Purpose General Purpose PCI Bus Applications Backplane SDRAM SDRAM
As designs become more complex and requirements more stringent, several application-specific I/O standards have emerged for specific applications. I/O standards for processors, memories, and a variety of bus applications have become commonplace and a requirement for many systems. In addition, I/O timing has
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QL6325E Eclipse-E Data Sheet Rev. F
become a greater issue with specific requirements for setup, hold, clock to out, and switching times. EclipseE has addressed these new system requirements and now includes a completely new I/O cell which consists of programmable I/Os as well as a new cell structure consisting of three registers--Input, Output, and OE. Eclipse-E offers banks of programmable I/Os that address many of the bus standards that are popular today. As shown in Figure 7 each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one output multiplexers. Figure 7: Eclipse-E I/O Cell
+ -
INPUT REGISTER
QE
D
R
OUTPUT REGISTER
D R
Q
PAD
OUTPUT ENABLE REGISTER
D
E
Q
R
The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown in Figure 7, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers. The select lines of the two-to-one multiplexers are static and must be connected to either VCC or GND. For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to be captured with fast set-up times without consuming internal logic cell resources. The comparator and multiplexor in the input path allows for native support of I/O standards with reference points offset from traditional ground. For output functions, I/O pins can receive combinatorial or registered data from the logic array. For combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For registered output operation, the array logic drives the D input of the output cell register which in turn drives
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QL6325E Eclipse-E Data Sheet Rev. F
the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the I/O pin. The addition of an output register will also decrease the Tco. Since the output register does not need to drive the routing the length of the output path is also reduced. The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the output cell. For combinatorial control operation data is routed from the logic array through a multiplexer to the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the same bank. For registered control operation, the array logic drives the D input of the OE cell register which in turn drives the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to be used for registered feedback into the logic array. I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/O's. The CLK and RESET signals share common lines, while the clock enables for each register can be independently controlled. I/O interface support is programmable on a per bank basis. The two Eclipse-E devices contain eight I/O banks. Figure 8 illustrates the I/O bank configurations. Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and INREF can be shared within the same bank (e.g., PCI and LVTTL). Figure 8: Multiple I/O Banks
VCCIO(F) INREF(F) VCCIO(E) INREF(E)
VCCIO(G)
PLL
Embedded RAM Blocks Embeded Computational Units
PLL
VCCIO(D)
INREF(G)
INREF(D)
Fabric
VCCIO(H) VCCIO(C)
INREF(H)
PLL
Embedded RAM Blocks
PLL
INREF (C)
VCCIO(A)
INREF(A)
VCCIO(B)
INREF(B)
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QL6325E Eclipse-E Data Sheet Rev. F
Programmable Slew Rate
Each I/O has programmable slew rate capability--the slew rate can be either fast or slow. The slower rate can be used to reduce the switching times of each I/O.
Programmable Weak Pull-Down
A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the need for external pull down resistors for used I/Os as shown in Figure 9. The spec for pull-down current is maximum of 150 A under worst case condition. Figure 9: Programmable I/O Weak Pull-Down
I/O Output Logic
PAD
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QL6325E Eclipse-E Data Sheet Rev. F
Clock Networks
Global Clocks
There are a maximum of eight global clock networks in each Eclipse-E device. Global clocks can drive logic cells and I/O registers, ECUs, and RAM blocks in the device. All global clocks have access to a Quad Net (local clock network) connection with a programmable connection to the logic cell's register clock input. Figure 10: Global Clock Architecture
Quad Net
Global Clock Net
CLK Pin
Quad-Net Network
There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is local to a quadrant. Before driving the columns clock buffers, the quad-net is driven by the output of a mux which selects between the CLK pin input and an internally generated clock source (see Figure 11). Figure 11: Global Clock Structure
Quad-Net Clock Network Internally generated clock, or clock from general routing network Global Clock (CLK) Input FF
Global Clock Buffer
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QL6325E Eclipse-E Data Sheet Rev. F
Dedicated Clock
There is one dedicated clock in the Eclipse-E Family (QL6250E and QL6325E). This clock connects to the clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global network with low skew. Users have the ability to select either the dedicated clock or the programmable clock (Figure 12). Figure 12: Dedicated Clock Circuitry within Logic Cell
Logic Cell
Programmable Clock or General Routing Dedicated Clock
CLK
NOTE: For more information on the clocking capabilities of Eclipse-E FPGAs, see QuickLogic Application Note 68 at http://www.quicklogic.com/images/appnote68.pdf.
I/O Control and Local Hi-Drives
Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant. These buffers can be driven by the internal logic both as an I/O control or high drive. For I/O constrained designs, these pins can be used for general purpose inputs. The performance of these resources is presented in Table 7. Table 7: I/O Control Network/Local High-Drive
Destination TT, 25 C, 2.5 V I/O (far) I/O (near) Skew From Pad 1.00 ns 0.63 ns 0.37 ns From Array 1.14 ns 0.78 ns 0.36 ns
Table 8 shows the total number of I/O control pins per device/package combination. Table 8: I/O Control Pins per Device/Package Combination
Device QL6325E 208 PQFP 16 280 LFBGA 16 484 BGA 16
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QL6325E Eclipse-E Data Sheet Rev. F
Programmable Logic Routing
Eclipse-E devices are engineered with six types of routing resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires supply VCC and GND (Logic `1' and Logic `0') to each column of logic cells. Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically used to implement intermediate length or medium fan-out nets. Express lines run the length of the programmable logic uninterrupted. Each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. The resistance will also be lower because the express wires don't require the use of "pass" links. Express wires provide higher performance for long routes or high fan-out nets. Distributed networks are described in Clock Networks on page 12. These wires span the programmable logic and are driven by quad-net buffers.
Global Power-On Reset (POR)
The Eclipse-E family of devices features a global power-on reset. This reset is hardwired to all registers and resets them to Logic `0' upon power-up of the device. In QuickLogic devices, the asynchronous Reset input to flip-flops has priority over the Set input; therefore, the Global POR will reset all flip-flops during power-up. If you want to set the flip-flops to Logic `1', you must assert the "Set" signal after the Global POR signal has been deasserted. Figure 13: Power-On Reset
VCC
Power-on Reset
Q
XXXXXXX
0
Low Power Mode
Quiescent power consumption of all Eclipse-E devices can be reduced significantly by de-activating the charge pumps inside the architecture. By applying 3.3 V to the VPUMP pin, the internal charge pump is deactivated--this effectively reduces the static and dynamic power consumption of the device. The Eclipse-E device is fully functional and operational in the Low Power mode. Users who have a 3.3 V supply available in their system should take advantage of this low power feature by tying the VPUMP pin to 3.3 V. Otherwise, if a 3.3 V supply is not available, this pin should be tied to ground.
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QL6325E Eclipse-E Data Sheet Rev. F
Joint Test Access Group (JTAG) Information
Figure 14: JTAG Block Diagram
TCK TMS TRSTB
Tap Controller State Machine (16 States)
Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
Mux
TDO
Bypass Register
Internal Register
I/O Registers
User Defined Data Register
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests: * Extest Instruction. The Extest Instruction performs a printed circuit board (PCB) interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (through the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed through a data scan operation, allowing users to sample the functional data entering and leaving the device.
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QL6325E Eclipse-E Data Sheet Rev. F
* Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device.
JTAG BSDL Support
* BSDL-Boundary Scan Description Language * Machine-readable data for test equipment to generate testing vectors and software * BSDL files available for all device/package combinations from QuickLogic * Extensive industry support available and ATVG (Automatic Test Vector Generation)
Security Links
There are several security links to disable reading logic from the array, and to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs. The option to program these links is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE.
Power-Up Loading Link
The flexibility link enables Power-Up Loading of the Embedded RAM blocks. If the link is programmed, the Power Up Loading state machine is activated during power-up of the device. The state machine communicates with an external EPROM via the JTAG pins to download memory contents into the on-chip RAM. If the link is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would. The option to program this link is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. For more information on Power-Up Loading, see QuickLogic Application Note 55 at http://www.quicklogic.com/images/appnote55.pdf. See the Power-Up Loading power-up sequencing requirement for proper functionality in Figure 15.
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 15: Required Power-Up Sequence When Using Power-Up Loading
V CCIO V DED V DED2 V PUMP V CC V CC PLL
Voltage
V CC
< 2 ms
Time
To use the power-up loading function, designers must ensure that VCC begins to ramp within a maximum of 2 ms of VCCIO, VDED, VDED2, and VPUMP.
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QL6325E Eclipse-E Data Sheet Rev. F
Electrical Specifications
DC Characteristics
The DC specifications are provided in Table 9 through Table 12. Table 9: Absolute Maximum Ratings
Parameter VCCPLL, VCC Voltage VCCIO Voltage INREF Voltage Input Voltage Value -0.5 V to 2.7V -0.5 V to 4.0 V 0.5 V to VCCIO -0.5 V to VCCIO +0.5 V Parameter Latch-up Immunity DC Input Current Leaded Package Storage Temperature Laminate Package (BGA) Storage Temperature Value 100 mA 20 mA -65 C to + 150 C -55 C to + 125 C
Table 10: Operating Range
Symbol Parameter Military Min 2.3 1.71 -55 -6 Speed Grade K Delay Factor -7 Speed Grade -8 Speed Grade 0.47 0.46 0.44 125 1.52 1.35 1.27 Max 2.7 3.6 Industrial Min 2.3 1.71 -40 0.48 0.47 0.45 Max 2.7 3.6 85 1.42 1.27 1.19 Commercial Min 2.3 1.71 0 0.51 0.50 0.48 Max 2.7 3.6 70 1.39 1.24 1.16 V V C C n/a n/a n/a Unit
VCCPLL, VCC Supply Voltage VCCIO TA TC I/O Input Tolerance Voltage Ambient Temperature Case Temperature
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Table 11: DC Characteristics
Symbol II IOZ CI CCLOCK IOS IDED IREF IPD ICCIO IPUMP IPLL ICC Parameter I or I/O Input Leakage Current 3-State Output Leakage Current I/O Input Capacitance
a
Conditions VI = VCCIO or GND VI = VCCIO or GND VO = GND VO = VCC VCC = 1.8 V VCCIO = 1.8 V VCCIO = 2.5 V VCCIO = 3.3 V VPUMP = 3.3 V 2.5 V VPUMP = 0 V VPUMP = 3.3 V
Min -10 -15 40 -10 -
Max 10 10 8 8 -180 210 10 50 10 10 20 3 10 -
Units A A pF pF mA mA A A A A A mA mA mA
Clock Input Capacitance Output Short Circuit Currentb D.C. Supply Current on VDED D.C. Supply Current on INREF Current on programmable pull-down D.C. Supply Current on VCCIO D.C. Supply Current on VPUMP D.C. Supply Current on each VCCPLL D.C. Supply Currentc, d
a. Capacitance is sample tested only. Clock pins are 12 pF maximum. b. Only one output at a time. Duration should not exceed 30 seconds. c. For -6/-7/-8 commercial grade devices only. Maximum ICC is 15 mA for all industrial grade devices and 25 mA for all military devices. d. ICC is for current drawn by VCC and VDED. If any PLLs are used, see Table 11 for current drawn by each PLL.
Table 12: DC Input and Output Levelsa
INREF VMIN LVTTL LVCMOS2 LVCMOS18 GTL+ PCI SSTL2 SSTL3 n/a n/a n/a 0.88 n/a 1.15 1.3 VMAX n/a n/a n/a 1.12 n/a 1.35 1.7 VMIN -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VIL VMAX 0.8 0.7 0.63 INREF - 0.2 0.3 x VCCIO INREF - 0.2 VMIN 2.2 1.7 1.2 INREF + 0.2 0.6 x VCCIO INREF + 0.2 VIH VMAX VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.5 VCCIO + 0.3 VCCIO + 0.3 VOL VMAX 0.4 0.7 0.7 0.6 0.74 1.10 VOH VMIN 2.4 1.7 1.7 n/a 1.76 1.90 IOL mA 2.0 2.0 2.0 40 7.6 8 IOH mA -2.0 -2.0 -2.0 n/a -0.5 -7.6 -8
0.1 x VCCIO 0.9 x VCCIO 1.5
INREF - 0.18 INREF + 0.18
a. The data provided in Table 12 are JEDEC and PCI specifications--QuickLogic devices either meet or exceed these requirements. For data specific to QuickLogic I/Os, see Table 17 through Table 22 and Figure 34 through
Figure 38. NOTE: For PQ208 package: All CLK, IOCTRL, and PLLIN pins are clamped to the VDED rail. Therefore, these pins can be driven up to VDED. All JTAG inputs are clamped to the VDED2 rail. These JTAG input pins can only be driven up to VDED2.
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QL6325E Eclipse-E Data Sheet Rev. F
NOTE: For PT280 and PS484 packages: All CLK, IOCTRL, and PLLIN pins are clamped to the VCCIO(C) rail. Therefore, these pins can be driven up to VCCIO(C). All JTAG inputs are clamped to the VDED2 rail. These JTAG input pins can only be driven up to VDED2. Figure 16 through Figure 19 show the VIL and VIH characteristics for I/O and clock pins. Figure 16: VIL Maximum for I/O
VILmax for IO
2.5 2 Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature
1.71 V 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V
Figure 17: VIH Minimum for I/O
VIHmin for IO
2.5 2 Voltage 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.71 V 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 18: VIL Maximum for CLOCK Pins
VILmax for CLOCK pins
2 1.71V Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V
Figure 19: VIH Minimum for CLOCK Pins
VIHmin for CLOCK pins
2.5 2 Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.71 V 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 20 through Figure 24 show the output drive characteristics for the I/Os across various voltages and temperatures. Figure 20: Drive Current at VCCIO = 1.71 V
Drive Current @ Vccio = 1.71 V
35 Drive Current (mA) 30 25 20 15 10 5 0 IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C
0. 4
0. 6
0. 8
1. 6
0. 2
1. 2
1. 4
0
1
Output Voltage (V)
Figure 21: Drive Current at VCCIO = 1.8 V
Drive Current @ Vccio = 1.8 V
40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Output Voltage (V)
1. 71
Drive Current (mA)
IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 22: Drive Current at VCCIO = 2.5 V
Drive Current @ Vccio = 2.5V
80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 Output Voltage (V)
Drive Current (mA)
IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C
Figure 23: Drive Current at VCCIO = 3.3 V
Drive Current @ Vccio = 3.3V
120
Drive Current (mA)
100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.3
Output Voltage (V)
IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 24: Drive Current at VCCIO = 3.6 V
Drive Current @ Vccio = 3.6V
140 Drive Current (mA) 120 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.3 3.6 Output Voltage (V) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C
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QL6325E Eclipse-E Data Sheet Rev. F
AC Characteristics*
*At VCC = 2.5 V, TA = 25C, Worst Case Corner, Speed Grade = -6 (K = 1.01). The AC Specifications are provided from Table 13 to Table 22. Logic cell diagrams and waveforms are provided from Figure 25 to Figure 38. Figure 25: Eclipse-E Logic Cell
Table 13: Logic Cell Delays
Symbol tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip-flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal must remain high/low Reset Width: time that the RESET signal must remain high/low Value Min 0.28 ns 0.10 ns 0 ns 0.22 ns 0.46 ns 0.46 ns 0.69 ns 1.09 ns 0.3 ns 0.3 ns Max 0.98 ns 0.25 ns 0 ns 0.52 ns 0.46 ns 0.46 ns 0.69 ns 1.09 ns 0.3 ns 0.3 ns
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 26: Logic Cell Flip-Flop
SET D CLK RESET Q
Figure 27: Logic Cell Flip-Flop Timings--First Waveform
CLK tCWHI (min) SET tCWLO (min)
RESET
Q tRESET tRW
tSET
tSW
Figure 28: Logic Cell Flip-Flop Timings--Second Waveform
CLK
D
tSU
tHL
Q
tCO
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 29: Eclipse-E Global Clock Structure
Quad net
Table 14: Eclipse-E Tree Clock Delay
Clock Segment tPGCK tBGCK tDPD tGSKEW tDSKEW Parameter Global clock pin delay to quad net Global clock tree delay (quad net to flip-flop) Dedicated clock pad Global delay clock skew Dedicated clock skew Value Min Max 1.92 ns 0.28 ns 1.7 ns 0.1 ns 0.05 ns
NOTE: When using a PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked Loop feedback path.
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 30: Global Clock Structure Timing Elements
Quad-Net Clock Network Internally generated clock, or clock from general routing network Global Clock (CLK) Input FF
Global Clock Buffer
Figure 31: RAM Module
[9:0] [17:0] WA WD WE WCLK RE RCLK RA RD ASYNCRD RAM Module [9:0] [17:0]
Table 15: RAM Cell Synchronous Write Timing
Symbol RAM Cell Synchronous Write Timing tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD 0.47 ns 0 ns 0.48 ns 0 ns 0 ns 0 ns 3.79 ns Parameter Value Min Max
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 32: RAM Cell Synchronous Write Timing
WCLK
WA tSWA WD tSWD WE tSWE RD old data tWCRD tHWE new data tHWD tHWA
Table 16: RAM Cell Synchronous and Asynchronous Read Timing
Symbol RAM Cell Synchronous Read Timing tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD RA to RD: time between when the READ ADDRESS is input and when the DATA is output 0.43 ns 0 ns 0.21 ns 0 ns 2.25 ns Parameter Value Min Max
RAM Cell Asynchronous Read Timing rPDRD 1.99 ns
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 33: RAM Cell Synchronous & Asynchronous Read Timing
RCLK
RA tSRA RE tSRE RD old data tHRE new data tHRA
tRCRD rPDRD
Figure 34: Eclipse-E Cell I/O
+ INPUT REGISTER
QE R
D
OUTPUT REGISTER
D R
Q
PAD
OUTPUT ENABLE REGISTER
D
EQ R
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 35: Eclipse-E Input Register Cell
tISU + tSID
QE R D
PAD
Table 17: I/O Input Register Cell Timing
Symbol tISU tIHL tICO tIRST tIESU tIEH Parameter Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock-to-out: time taken by the flip-flop to output after the active clock edge Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge Value Min 2.15 ns 0 ns 0.4 ns 0 ns Max 0.3 ns 0.82 ns -
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QL6325E Eclipse-E Data Sheet Rev. F
Table 18: I/O Input Buffer Delays
Parameter Symbol To get the total input delay add this delay to tISU tSID (LVTTL) tSID (LVCMOS2) LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications Min Max 0.82 ns 0.82 ns 0.94 ns 0.94 ns 0.94 ns 0.82 ns Value
tSID (LVCMOS18) LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications tSID (GTL+) tSID (SSTL3) tSID (SSTL2) tSID (PCI) GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5 V PCI input delay: Peripheral Component Interconnect for 3.3 V
Figure 36: Eclipse-E Input Register Cell Timing
R
CLK
D
tISU
t t
IHL ICO t IRST
Q
E
t IESU t IEH
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 37: Eclipse-E Output Register Cell
PAD OUTPUT REGISTER
Table 19: Eclipse-E I/O Cell Output Timing Symbol Output Register Cell Only tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-state Output Delay low to tri-state Clock-to-out delay (does not include clock tree delays) Parameter 4.0 3.5 4.96 4.87 5.8 5.58 5.49 Value (ns) Slow Slew Max Fast Slew Max 2.95 2.49 2.93 2.84 3.62 3.4 3.3
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 38: Eclipse-E Output Register Cell Timing
H L H Z L H Z L
tOUTLH
H L H tPZH Z L H Z L
tOUTHL
tPZL tPHZ
tPLZ
Table 20: Output Slew Rates @ VCCIO = 3.3 V
Fast Slew Rising Edge Falling Edge 2.8 V/ns 2.86 V/ns Slow Slew 1.0 V/ns 1.0 V/ns
Table 21: Output Slew Rates @ VCCIO = 2.5 V
Fast Slew Rising Edge Falling Edge 1.7 V/ns 1.9 V/ns Slow Slew 0.6 V/ns 0.6 V/ns
Table 22: Output Slew Rates @ VCCIO = 1.8 V
Fast Slew Rising Edge Falling Edge - V/ns - V/ns Slow Slew - V/ns - V/ns
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QL6325E Eclipse-E Data Sheet Rev. F
Package Thermal Characteristics
Thermal Resistance Equations:
JC = (TJ - TC)/P JA = (TJ - TA)/P
PMAX = (TJMAX - TAMAX)/ Parameter Description:
JA
JC: Junction-to-case thermal resistance JA: Junction-to-ambient thermal resistance
TJ: Junction temperature TA: Ambient temperature P: Power dissipated by the device while operating PMAX: The maximum power dissipation for the device TJMAX: Maximum junction temperature TAMAX: Maximum ambient temperature NOTE: Maximum junction temperature (TJMAX) is 150 C. To calculate the maximum power dissipation for a device package look up JA from Table 23, pick an appropriate TAMAX and use: PMAX = (150 C - TAMAX)/
JA
Table 23: Package Thermal Characteristics
Device
Package Description Package Code Package Type PS PBGA LFBGA PQFP PT PQ Pin Count 484 280 208 0 LFM 26.6 34 32
JA ( C/W)
200 LFM 24.1 13.6 28 400 LFM 21.8 29.9 26.5
QL6325E
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QL6325E Eclipse-E Data Sheet Rev. F
Kv and Kt Graphs
Figure 39: Voltage Factor vs. Supply Voltage
Voltage Factor vs Supply Voltage
1.3 1.28 1.26 1.24 1.22 Kv 1.2 1.18 1.16 1.14 1.12 1.1 2.25 2.35 2.45 2.5 2.55 2.65 2.75 Supply Voltage (V) Kv
Figure 40: Temperature Factor vs. Operating Temperature
Temperature Factor vs. Operating Temperature
1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 -60 -55 -40 0 25 85 125 130 Junction Temperature (C) Kt Kt
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QL6325E Eclipse-E Data Sheet Rev. F
Power vs. Operating Frequency
The basic power equation which best models power consumption is given below: PTOTAL = 0.350 + f[0.0031 LC + 0.0948 CKBF + 0.01 CLBF + 0.0263 0.543 RAM + 0.20 PLL + 0.0035 INP + 0.0257 OUTP] (mW) Where:
CKLD +
LC is the total number of logic cells in the design CKBF = # of clock buffers CLBF = # of column clock buffers CKLD = # of loads connected to the column clock buffers RAM = # of RAM blocks PLL = # of PLLs INP is the number of input pins OUTP is the number of output pins
NOTE: To learn more about power consumption, see QuickLogic Application Note 60 at http://www.quicklogic.com/images/appnote60.pdf.
Power-Up Sequencing
Figure 41: Power-Up Sequencing
VCCIO VDED VDED2 VPUMP VCC
|VCCIO, VDED, VDED2, VPUMP - VCC|MAX
Voltage
VccPLL
VCC
400 us
Time
When powering up a device, the VCCPLL/VCC/VCCIO/VDED/VDED2 rails must take 400 s or longer to reach the maximum value (refer to Figure 41). NOTE: Ramping VCCPLL, VCC, VCCIO, VPUMP, VDED, or VDED2 faster than 400 s can cause the device to behave improperly. For users with a limited power budget, ensure VCCIO, VDED, VDED2, and VPUMP are within 500 mV of VCC when ramping up the power supplies.
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QL6325E Eclipse-E Data Sheet Rev. F
PQ208 Pin Descriptions
Table 24: PQ208 Pin Descriptions
Pin Direction Function JTAG Pin Descriptions TDI/RSI TRSTB/RRO TMS TCK TDO/RCO I I/0 I I O Test Data In for JTAG/RAM init. Serial Data In Active low Reset for JTAG/RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VDED2 if unused Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused Hold HIGH during normal operation. Connect to VDED2 if not used for JTAG Hold HIGH or LOW during normal operation. Connect to VDED2 or GND if not used for JTAG Description
Connect to serial PROM clock for RAM initialization. Must be Test data out for JTAG/RAM init. left unconnected if not used for JTAG or RAM initialization. clock out The output voltage drive is specified by VDED. Dedicated Pin Descriptions Low skew global clock. This pin provides access to a dedicated, distributed network capable of driving the CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, CLOCK of the ECUs, and Output Enables of the I/Os. The voltage tolerance of this pin is specified by VDED. The I/O pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-directional pin. The A inside the parenthesis means that the I/O is located in Bank A. If an I/O is not used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState. Connect to 2.5 V supply.
CLK
I
Global clock network pin
I/O(A)
I/O
Input/Output pin
VCC
I
Power supply pin
VCCIO(A)
I
This pin provides the flexibility to interface the device with either a 3.3 V, 2.5 V, or 1.8 V device. The A inside the parenthesis means that VCCIO is located in BANK A. Every Input voltage tolerance/drive pin I/O pin in Bank A will be tolerant of VCCIO input signals and will drive VCCIO level output signals. This pin must be connected to either 3.3 V, 2.5 V, or 1.8 V. Ground pin PLL clock input Connect to ground. Clock input for PLL. The voltage tolerance of this pin is specified by VDED. Very low skew global clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g., RAM, Flip Flops). The voltage tolerance of this pin is specified by VDED. Connect to GND.
GND PLLIN
I I
DEDCLK
I
Dedicated clock pin
GNDPLL
I
Ground pin for PLL
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QL6325E Eclipse-E Data Sheet Rev. F
Table 24: PQ208 Pin Descriptions (Continued)
Pin Direction Function Description The INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. Follow the recommendations provided in Table 12 for the appropriate standard. The A inside the parenthesis means that INREF is located in BANK A. This pin should be tied to GND if voltage referenced standards are not used. Dedicated PLL output pin. Must be left unconnected if the PLL is not driven off chip. PLLOUT pin is driven by VCCIO. For a list of each PLLOUT pin and the VCCIO pin that powers it see Table 26. This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a highdrive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in Bank A. There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not used. For backwards compatibility with Eclipse and EclipsePlus, it can be tied to VDED or GND. If tied to VDED, it will draw no more than 20 A per IOCTRL pin due to the pulldown resistor. The voltage tolerance of this pin is specified by VDED. This pin disables the internal charge pump for lower static power consumption. To disable the charge pump, connect VPUMP to 3.3 V. If the Disable Charge Pump feature is not used, connect VPUMP to GND. For backwards compatibility with Eclipse and EclipsePlus devices, connect VPUMP to GND. This pin specifies the input voltage tolerance for CLK, DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well as the output voltage drive TDO JTAG pins. If the PLLs are used, VDED must be 2.5 V or 3.3 V. The legal range for VDED is between 1.71 V and 3.6 V. For backwards compatibility with Eclipse and EclipsePlus devices, connect VDED to 2.5 V. These pins specify the input voltage tolerance for the JTAG input pins. The legal range for VDED2 is between 1.71 V and 3.6 V. These do not specify output voltage of the JTAG output, TDO. Refer to the VDED pin section for specifying the JTAG output voltage. VDED2 must be egual to or greater than VDED. Connect to 2.5 V supply. Even if your design does not utilize the PLLs, you must connect VCCPLL to 2.5 V. If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. If a PLL module is not used, then the associated PLLRST must be connected to VDED.
INREF(A)
I
Differential reference voltage
PLLOUT
O
PLL output pin
IOCTRL(A)
I
Highdrive input
VPUMP
I
Charge Pump Disable
VDED
I
Voltage tolerance for clocks, TDO JTAG output, and IOCTRL
VDED2
I
Voltage tolerance for JTAG pins (TDI, TMS, TCK, and TRSTB)
VCCPLL
I
Power Supply pin for PLL
PLL_RESET
I
PLL reset pin
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QL6325E Eclipse-E Data Sheet Rev. F
PT280 and PS484 Pin Descriptions
Table 25: PT280 and PS484 Pin Descriptions
Pin Direction Function JTAG Pin Descriptions TDI/RSI I Test Data In for JTAG/RAM init. Serial Data In Active low Reset for JTAG/RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VDED2 if unused Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused Hold HIGH during normal operation. Connect to VDED2 if not used for JTAG Hold HIGH or LOW during normal operation. Connect to VDED2 or GND if not used for JTAG Description
TRSTB/RRO TMS TCK
I/0 I I
TDO/RCO
O
Connect to serial PROM clock for RAM initialization. Must be Test data out for JTAG/RAM init. left unconnected if not used for JTAG or RAM initialization. clock out The output voltage drive is specified by VCCIO(C). Dedicated Pin Descriptions Low skew global clock. This pin provides access to a dedicated, distributed network capable of driving the CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, CLOCK of the ECUs, and Output Enables of the I/Os. The voltage tolerance of this pin is specified by VCCIO(C). Very low skew global clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g., RAM, Flip Flops). The voltage tolerance of this pin is specified by VCCIO(C). Connect to ground. Connect to GND. The INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. Follow the recommendations provided in Table 12 for the appropriate standard. The A inside the parenthesis means that INREF is located in BANK A. This pin should be tied to GND if voltage referenced standards are not used. The I/O pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-directional pin. The A inside the parenthesis means that the I/O is located in Bank A. If an I/O is not used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState.
CLK
I
Global clock network pin
DEDCLK
I
Dedicated clock pin
GND GNDPLL
I I
Ground pin Ground pin for PLL
INREF(A)
I
Differential reference voltage
I/O(A)
I/O
Input/Output pin
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QL6325E Eclipse-E Data Sheet Rev. F
Table 25: PT280 and PS484 Pin Descriptions (Continued)
Pin Direction Function Description This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a highdrive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in Bank A. There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not used. For backwards compatibility with Eclipse and EclipsePlus, it can be tied to VCCIO(C) or GND. If tied to VCCIO(C), it will draw no more than 20 A per IOCTRL pin due to the pulldown resistor. The voltage tolerance of this pin is specified by VCCIO(C). Clock input for PLL. The voltage tolerance of this pin is specified by VCCIO(C). Dedicated PLL output pin. Must be left unconnected if the PLL is not driven off chip. PLLOUT pin is driven by VCCIO. For a list of each PLLOUT pin and the VCCIO pin that powers it see Table 26. Connect to 2.5 V supply. This pin specifies the input voltage tolerance for CLK, DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well as the output voltage drive TDO JTAG pins. If the PLLs are used, VCCIO(C) must be 2.5 V or 3.3 V. The legal range for VCCIO(C) is between 1.71 V and 3.6 V.
IOCTRL(A)
I
Highdrive input
PLLIN
I
PLL clock input
PLLOUT
O
PLL output pin
VCC
I
Power supply pin
VCCIO(C)
I
Voltage tolerance for clocks, TDO JTAG output, and IOCTRL. This pin provides the flexibility to interface the device with Input voltage tolerance/drive pin. either a 3.3 V, 2.5 V, or 1.8 V device. The C inside the parenthesis means that VCCIO is located in BANK C. Every I/O pin in Bank C will be tolerant of VCCIO input signals and will drive VCCIO level output signals. This pin must be connected to either 3.3 V, 2.5 V, or 1.8 V. This pin provides the flexibility to interface the device with either a 3.3 V, 2.5 V, or 1.8 V device. As an exmple, the A inside the parenthesis means that VCCIO is located in BANK Input voltage tolerance/drive pin A. Every I/O pin in Bank A will be tolerant of VCCIO input signals and will drive VCCIO level output signals. This pin must be connected to either 3.3 V, 2.5 V, or 1.8 V. Power Supply pin for PLL Connect to 2.5 V supply. Even if your design does not utilize the PLLs, you must connect VCCPLL to 2.5 V. If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. If a PLL module is not used, then the associated PLLRST must be connected to VCCIO(C).
VCCIO(A), VCCIO(B), VCCIO(D), VCCIO(E), VCCIO(F), VCCIO(G), VCCIO(H) VCCPLL
I
I
PLL_RESET
I
PLL reset pin
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41
QL6325E Eclipse-E Data Sheet Rev. F
Table 25: PT280 and PS484 Pin Descriptions (Continued)
Pin VDED Direction I No connect Function Description This pin may be left unconnected. See pin VCCIO(C) for more information. These pins specify the input voltage tolerance for the JTAG input pins. The legal range for VDED2 is between 1.71 V and 3.6 V. These do not specify output voltage of the JTAG output, TDO. Refer to the VCCIO(C) pin section for specifying the JTAG output voltage. VDED2 must be equal to or greater than VCCIO(C). This pin disables the internal charge pump for lower static power consumption. To disable the charge pump, connect VPUMP to 3.3 V. If the Disable Charge Pump feature is not used, connect VPUMP to GND. For backwards compatibility with Eclipse and EclipsePlus devices, connect VPUMP to GND.
VDED2
I
Voltage tolerance for JTAG pins (TDI, TMS, TCK, and TRSTB)
VPUMP
I
Charge Pump Disable
Table 26: PLLOUT Pin Supply Voltage
PLLOUT PLLOUT(0) PLLOUT(1) PLLOUT(2) PLLOUT(3) VCCIO VCCIO(E) VCCIO(B) VCCIO(A) VCCIO(F)
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QL6325E Eclipse-E Data Sheet Rev. F
Figure 42: I/O Banks with Relevant Pins
IOCTRL(A) VCCIO (A) INREF(A) VCCIO (A) INREF(A) IOCTRL(A)
IO(A)
IO BANK A VCCIO (H) INREF(H) IOCTRL(H) IO(H)
IO BANK B VCCIO (C) INREF(C) IOCTRL(C) IO(C)
IO BANK H
IO(A)
IO BANK C
IO BANK G
VCCIO (G) INREF(G) IOCTRL(G) IO(G)
VCCIO (D) INREF(D) IOCTRL(D) IO(D)
IO BANK D
IO BANK F
IO BANK E
INREF(E)
IO(E)
INREF(F)
IO(F)
VCCIO (E)
IOCTRL(E)
Recommended Unused Pin Terminations for Eclipse-E Devices
All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint > Fix Placement in the Option pull-down menu of SpDE.
VCCIO (F)
IOCTRL(F)
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43
QL6325E Eclipse-E Data Sheet Rev. F
The rest of the PQ208 pins should be terminated at the board level in the manner presented in Table 27. Table 27: PQ208 Recommended Unused Pin Terminations
Signal Name Recommended Termination In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 m devices. For Rev. G (and later) silicon, unused PLLOUT pins should be left unconnected. Used PLLOUT pins will normally be connected to inputs, but can also be left unconnected. For the truth table of PLLOUT connections, refer to Table 29. There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not used. For backwards compatibility with Eclipse, it can be tied to VDED or GND. If tied to VDED, it will draw no more than 20 A per IOCTRL pin due to the pulldown resistor. Any unused clock pins should be connected to VDED or GND. If a PLL module is not used, then the associated PLLRST must be connected to VDED. If an I/O bank does not require the use of the INREF signal the pin should be connected to GND.
PLLOUTa
IOCTRLb CLK/PLLIN PLLRST INREF
a. x represents a number. b. y represents an alphabetical character.
The rest of the PT280 and PS484 pins should be terminated at the board level in the manner presented in Table 28. Table 28: PT280 and PS484 Recommended Unused Pin Terminations
Signal Name Recommended Termination In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 m devices. For Rev. G (and later) silicon, unused PLLOUT pins should be left unconnected. Used PLLOUT pins will normally be connected to inputs, but can also be left unconnected. For the truth table of PLLOUT connections, refer to Table 29. There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not used. For backwards compatibility with Eclipse, it can be tied to VCCIO(C) or GND. If tied to VCCIO(C), it will draw no more than 20 A per IOCTRL pin due to the pulldown resistor. Any unused clock pins should be connected to VCCIO(C) or GND. If a PLL module is not used, then the associated PLLRST must be connected to VCCIO(C). If an I/O bank does not require the use of the INREF signal the pin should be connected to GND.
PLLOUTa
IOCTRLb CLK/PLLIN PLLRST INREF
a. x represents a number. b. y represents an alphabetical character.
Table 29: Recommended PLLOUT Terminations Truth Table
PLL_RESET 0 1 Recommend PLLOUT Termination Must be left unconnected. May be left unconnected, or connected to GND. Must not be connected to VCC.
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QL6325E Eclipse-E Data Sheet Rev. F
208 PQFP Pinout Diagram
Eclipse-E
QL6325E-6PQ208C
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45
QL6325E Eclipse-E Data Sheet Rev. F
208 PQFP Pinout Table
Table 30: 208 PQFP Pinout Table
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Function PLLRST(3) VCCPLL(3) GND GND I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) IOCTRL(A) VCC INREF(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) GND I/O(A) TDI CLK(0) CLK(1) VCC CLK(2)/PLLIN(2) CLK(3)/PLLIN(1) VDED CLK(4) DEDCLK PLLIN(0) I/O(B) I/O(B) GND VCCIO(B) I/O(B) I/O(B) I/O(B) I/O(B) IOCTRL(B) INREF(B) IOCTRL(B) I/O(B) Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Function I/O(B) VCCIO(B) I/O(B) VCC I/O(B) I/O(B) GND TDO PLLOUT(1) GNDPLL(2) GND VCCPLL(2) PLLRST(2) VDED I/O(C) GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) IOCTRL(C) INREF(C) IOCTRL(C) I/O(C) I/O(C) VCCIO(C) I/O(C) I/O(C) GND VCC I/O(C) TRSTB VDED2 I/O(D) I/O(D) I/O(D) GND VCCIO(D) Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Function I/O(D) VCC I/O(D) I/O(D) VCC I/O(D) I/O(D) IOCTRL(D) INREF(D) IOCTRL(D) I/O(D) I/O(D) I/O(D) VCCIO(D) I/O(D) I/O(D) VPUMP PLLOUT(0) GND GNDPLL(1) PLLRST(1) VCCPLL(1) I/O(E) GND I/O(E) I/O(E) VCCIO(E) I/O(E) VCC I/O(E) I/O(E) I/O(E) IOCTRL(E) INREF(E) IOCTRL(E) I/O(E) I/O(E) VCCIO(E) GND I/O(E) I/O(E) I/O(E) Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Function CLK(5)/PLLIN(3) CLK(6) VDED CLK(7) VCC CLK(8) TMS I/O(F) I/O(F) I/O(F) GND VCCIO(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) IOCTRL(F) INREF(F) VCC IOCTRL(F) I/O(F) I/O(F) VCCIO(F) I/O(F) I/O(F) GND I/O(F) PLLOUT(3) GNDPLL(0) GND VCCPLL(0) PLLRST(0) GND I/O(G) VCCIO(G) I/O(G) I/O(G) VCC I/O(G) I/O(G) I/O(G) Pin 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function IOCTRL(G) INREF(G) IOCTRL(G) I/O(G) I/O(G) I/O(G) VCC I/O(G) VCCIO(G) GND I/O(G) I/O(G) I/O(G) VCC TCK VDED2 I/O(H) I/O(H) I/O(H) GND VCCIO(H) I/O(H) I/O(H) IOCTRL(H) I/O(H) INREF(H) VCC IOCTRL(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) VCCIO(H) GND I/O(H) PLLOUT(2) GND GNDPLL(3)
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QL6325E Eclipse-E Data Sheet Rev. F
280 LFBGA Pinout Diagram
Top
Eclipse-E QL6325E-6PT280C
Bottom
Pin A1 Corner
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47
QL6325E Eclipse-E Data Sheet Rev. F
280 LFBGA Pinout Table
Table 31: 280 LFBGA Pinout Table
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function PLLOUT(3) GNDPLL(0) I/O(F) I/O(F) I/O(F) IOCTRL(F) I/O(F) I/O(F) I/O(F) CLK(7) I/O(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) PLLRST(1) GND PLLRST(0) GND I/O(F) I/O(F) I/O(F) INREF(F) I/O(F) I/O(F) TMS CLK(6) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) VCCPLL(1) GNDPLL(1) PLLOUT(0) I/O(F) VCCPLL(0) I/O(F) I/O(F) VCCIO(F) IOCTRL(F) I/O(F) I/O(F) VCCIO(F) Ball C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 Function CLK(5)/ PLLIN(3) VCCIO(E) I/O(E) I/O(E) I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(G) I/O(G) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) CLK(8) I/O(E) I/O(E) I/O(E) INREF(E) I/O(E) I/O(E) I/O(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) VCCIO(G) I/O(F) GND VCC VCC VDED VCC GND GND VCC VCC GND VPUMP I/O(D) VCCIO(D) INREF(D) Ball E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 Function IOCTRL(D) INREF(G) IOCTRL(G) I/O(G) I/O(G) GND VCC IOCTRL(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) IOCTRL(G) I/O(G) VCC VCC I/O(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) I/O(G) I/O(G) VCC VCC VDED2 I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) VCCIO(G) I/O(G) GND VCC I/O(C) VCCIO(D) I/O(D) I/O(D) VDED2 TCK I/O(G) I/O(G) GND GND Ball K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 Function I/O(C) I/O(D) I/O(C) TRSTB I/O(H) I/O(H) VCCIO(H) I/O(H) VCC GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(H) I/O(H) I/O(H) I/O(H) VCC VDED INREF(C) I/O(C) I/O(C) I/O(C) IOCTRL(H) I/O(H) I/O(H) I/O(H) VCC VCC I/O(C) I/O(C) IOCTRL(C) IOCTRL(C) I/O(H) I/O(H) IOCTRL(H) INREF(H) VCC GND I/O(C) I/O(C) I/O(C) I/O(C) I/O(H) I/O(H) VCCIO(H) Ball R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Function I/O(H) GND GND VCC VCC GND GND VCC VCC VCC VDED GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(H) I/O(H) I/O(A) I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) CLK(3)/ PLLIN(1) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCPLL(2) I/O(B) I/O(B) I/O(A) I/O(A) VCCPLL(3) I/O(A) VCCIO(A) INREF(A) I/O(A) I/O(A) VCCIO(A) CLK(0) VCCIO(B) I/O(B) Ball U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function I/O(B) IOCTRL(B) VCCIO(B) I/O(B) TDO PLLRST(2) I/O(B) PLLOUT(2) GNDPLL(3) GND I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) CLK(1) CLK(4)/ DEDCLK/ PLLIN(0) I/O(B) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) GNDPLL(2) GND GND PLLRST(3) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) TDI CLK(2)/ PLLIN(2) I/O(B) I/O(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(B) I/O(B) PLLOUT(1)
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QL6325E Eclipse-E Data Sheet Rev. F
484 PBGA Pinout Diagram
Top
Eclipse-E QL6325E-6PS484C
Bottom
Pin A1 Corner
A B C D E F G H J K L M N P R T U V W Y AA AB
22
21 20
19 18
17 16
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
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49
QL6325E Eclipse-E Data Sheet Rev. F
484 PBGA Pinout Table
Table 32: 484 PBGA Pinout Table
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 Function I/O(A) PLLRST(3) I/O(A) I/O(A) I/O(A) I/O(H) I/O(H) IOCTRL(H) I/O(H) NC NC TCK I/O(G) I/O(G) I/O(G) I/O(G) I/O(G) I/O(G) I/O(F) GND PLLOUT(3) I/O(F) I/O(A) GND GNDPLL(3) GND I/O(A) I/O(H) I/O(H) INREF(H) I/O(H) I/O(H) I/O(H) NC NC NC I/O(G) I/O(G) I/O(G) I/O(G) PLLRST(0) I/O(F) I/O(F) I/O(F) Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 Function I/O(A) I/O(A) VCCPLL(3) PLLOUT(2) I/O(A) I/O(H) I/O(H) I/O(H) IOCTRL(H) I/O(H) I/O(H) I/O(H) I/O(G) I/O(G) I/O(G) I/O(G) I/O(G) I/O(G) I/O(F) GNDPLL(0) I/O(F) I/O(F) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(G) I/O(G) I/O(G) IOCTRL(G) I/O(G) I/O(G) I/O(F) VCCPLL(0) I/O(F) I/O(F) I/O(F) Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 Function IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(H) NC I/O(H) I/O(H) I/O(H) VDED2 I/O(G) I/O(G) I/O(G) IOCTRL(G) I/O(G) INREF(G) I/O(G) I/O(F) I/O(F) I/O(F) I/O(F) I/O(A) INREF(A) I/O(A) I/O(A) I/O(A) VCCIO(A) VCCIO(H) I/O(H) VCCIO(H) I/O(H) VCCIO(H) VCCIO(G) I/O(G) VCCIO(G) NC VCCIO(G) NC I/O(F) I/O(F) IOCTRL(F) I/O(F) IOCTRL(F) Ball G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 Function I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) GND I/O(H) I/O(H) I/O(H) I/O(G) GND I/O(G) I/O(G) I/O(G) VPUMP VCCIO(F) I/O(F) I/O(F) I/O(F) INREF(F) I/O(F) I/O(A) I/O(A) I/O(A) I/O(A) IOCTRL(A) VCCIO(A) I/O(H) GND VCC VCC VDED GND VCC VCC GND I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) Ball J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 Function I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCC GND VCC VCC GND VCC GND VCC I/O(F) VCCIO(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) TDI I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) VCC VCC GND GND GND GND VCC VCC I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) Ball L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 Function CLK(4)/ DEDCLK/ PLLIN(0) CLK(0) CLK(2)/PLLIN(2) I/O(A) I/O(A) I/O(A) GND GND GND GND GND GND GND VCC VCC CLK(6) VCCIO(F) I/O(F) CLK(8) I/O(F) I/O(F) I/O(F) I/O(B) I/O(B) I/O(B) CLK(3)/PLLIN(1) I/O(B) VCCIO(B) CLK(1) VCC VCC GND GND GND GND GND GND GND I/O(E) I/O(E) I/O(E) CLK(7) CLK(5)/PLLIN(3) TMS
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QL6325E Eclipse-E Data Sheet Rev. F
Table 32: 484 PBGA Pinout Table (Continued)
Ball N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Function I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCC VCC GND GND GND GND VCC VCC I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) VCC GND VCC GND VCC VCC GND VDED Ball P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 Function I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) GND VCC VCC GND VDED VCC VCC GND I/O(D) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) GND I/O(C) Ball T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 Function NC TRSTB GND NC I/O(D) NC I/O(D) GND I/O(E) I/O(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) IOCTRL(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(C) VCCIO(C) NC VCCIO(C) I/O(C) VCCIO(C) VCCIO(D) I/O(D) VCCIO(D) NC VCCIO(D) VCCIO(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) INREF(E) I/O(B) Ball V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 Function I/O(B) I/O(B) I/O(B) I/O(B) I/O(C) I/O(C) I/O(C) NC I/O(C) I/O(C) VDED2 NC I/O(D) I/O(D) INREF(D) I/O(D) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(C) NC I/O(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) NC Ball W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 Function I/O(D) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) VCCPLL(2) I/O(C) I/O(C) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) PLLOUT(0) PLLRST(1) I/O(E) I/O(E) TDO PLLOUT(1) GND I/O(B) I/O(C) I/O(C) I/O(C) INREF(C) I/O(C) Ball AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Function I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(E) GNDPLL(1) I/O(E) I/O(E) I/O(B) GNDPLL(2) PLLRST(2) I/O(B) I/O(B) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) GND VCCPLL(1) I/O(E)
(c) 2005 QuickLogic Corporation
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QL6325E Eclipse-E Data Sheet Rev. F
Package Mechanical Drawings
208 PQFP Packaging Drawing
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(c) 2005 QuickLogic Corporation
QL6325E Eclipse-E Data Sheet Rev. F
280 LFBGA Packaging Drawing
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
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QL6325E Eclipse-E Data Sheet Rev. F
484 PBGA Packaging Drawing
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(c) 2005 QuickLogic Corporation
QL6325E Eclipse-E Data Sheet Rev. F
Packaging Information
The Eclipse-E product family packaging information is presented in Table 33. NOTE: Military temperature range plastic packages will be added as follow on products to the commercial and industrial products. Table 33: Packaging Options
QL6325E Device Information Pin/Ball 208 PQFP Package Definitionsa 280 LFBGA 484 BGA Pitch 0.50 mm 0.80 mm 1.0 mm
a. PQFP = Plastic Quad Flat Pack BGA = Ball Grid Array LFBGA = Low Profile Fine Pitch Ball Grid Array
Ordering Information
QL 6325E - 6 PQ208 C QuickLogic device Eclipse-E device part number Speed Grade 6 = Fast 7 = Faster 8 = Fastest Operating Range C = Commercial I = Industrial M = Military Package Code PQ208 (PQN208)* = 208-pin PQFP PT280 (PTN280)* = 280-pin LFBGA (0.8 mm) PS484 = 484-pin BGA (1.0 mm)
* Lead-free packaging is available, contact QuickLogic regarding availability (see Contact Information).
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
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QL6325E Eclipse-E Data Sheet Rev. F
Contact Information
Phone: (408) 990-4000 (US) (416) 497-8884 (Canada) +(44) 1932 57 9011 (Europe - except Germany/Benelux) +(49) 89 930 86 170 (Germany/Benelux) +(86) 21 6867 0273 (Asia - except Japan) +(81) 45 470 5525 (Japan) E-mail: Sales: info@quicklogic.com www.quicklogic.com/sales
Support: www.quicklogic.com/support Internet: www.quicklogic.com
Revision History
Revision A B C D E F Date December 2002 July 2003 November 2003 June 2004 October 2004 March 2005 Comments Brian Faith and Andreea Rotaru Brian Faith and Kathleen Murchek Bernhard Andretzky and Kathleen Murchek Brian Faith, Mehul Kochar and Kathleen Murchek Brian Faith, Mehul Kochar and Kathleen Murchek Brian Faith, Mehul Kochar and Kathleen Murchek
Copyright and Trademark Information
Copyright (c) 2005 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, Eclipse II, EclipseE, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
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(c) 2005 QuickLogic Corporation

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